Series Termination on clock signals

Here is a simple snapshot of the circuit and the clock signal with and without series termination. Simulation is done in HyperLynx. 

Without Series termination:

We randomly considered a driver and a receiver and assigned ibis model that is available within the HyperLynx. The pre-layout is considered to have:

• 6-layer stack up
• signal routed in both strip line and micro strip line configuration
• signal routed from top layer to the Layer#3 using a VIA from the top layer
• signal routed back to top layer from Layer#3 using a VIA
• There are 2 receivers considered

Definitely with the VIA introduced there is a impedance mismatch and the circuit output simulation output looks like:

With Series termination:

To improve this we randomly considered a series termination resistor

We can see that a series resistor of 33 ohms is introduced at the source side.

Once simulated, the waveform looks as below:

We can see that definitely, there is a improvement in the signal. Not as expected though :-)

Note: This example was just considered to show how the simulation looks like with series resistor introduced and definitely thorough technical analysis is not done and even the models are not considered accurately.