- As speed increases with each generation of DDR, timings have reduced and boards are prone to signal integrity issues. It is important that designer chooses a right routing topology for the generation of DDR they are using in their circuit.
- DDR3 and DDR4 Memory uses Fly-By Topology
- DDR2 Memory uses Symmetrical T-Topology
- DDR1 Memory uses Asymmetrical T-Topology
- The major advantage of Fly-By Topology is that stub lengths are reduced, routing is clean and improves signal integrity
- The routing on PCB follows JEDEC standards
- CLOCK, COMMAND, CONTROL, ADDRESS signals follow Fly-By topology
- CLOCK, COMMAND, CONTROL, ADDRESS signals follow T topology
- DATA is routed one to one lanes wise from Memory Controller to DRAM chips
- Write-Leveling is used for DDR3/DDR4 to adjust the skew between the clock and data strobe signals
- While skew is disadvantage in terms of timing and is compensated by write-leveling, the introduced skew provides advantages interms of noise. The Simultaneous switching noise (SSN) which can be generated is reduced as there is reduced simultaneous switching of strobe and clock signals.
- A termination resistor is used at the end of the chain to absorb reflections and hence improve signal integrity
Access the video from our YouTube channel on the same using below link:
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