This is one of the question that came up while having a discussion on high speed designs. One of the engineer asked this question - While working on high speed designs, we do follow the guidelines suggested by the manufacturers, we also apply rules as per our previous learning. If a situation arises where we cannot apply all the rules, what should be our approach?
While implementing all the design rules and recommendations is must, it is not always practical to implement all the rules on the PCB. The PCB constraints, need to allow other interfaces/power to be implemented, pushes PCB layout engineer to a limit. In a scenario, where all of these cannot be implemented, following approach has to be taken:
- List the critical sections that might cause most signal integrity issues. Priority is to apply all the rules to these sections. Ensure that these are routed first and then other sections are followed
- While routing the PCB Layout engineer has to consult deign engineer on a regular basis and explain about the deviations taken
- Design engineer has to ensure that all these are simulated by some means to ensure that design is good to release. It is important that design engineer and PCB Layout engineer has to and fro communication and risks are documented properly. Any trouble creators that escape this phase can lead to project delays
- There are scenarios, where design engineers do take a risk of releasing the board with marginal signal integrity analysis pass scenarios. This is a calculated risk by the designers as there could be very minimal possibility of improving the board routing scenarios. The design engineers are left with no choice but to take risk
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