Understanding the DDR4 Memory - Part 1

 

It is important that we understand the major features of memories like DDR4. Let us look at some of the major changes of DDR4 w.r.t DDR3 at the interface level.

Operating Voltage:

The operating voltage of DDR4 is 1.2V. As per JEDEC specification, the voltage tolerance is ±60mV.

Voltage Pump (VPP):

While DDR3 generates this rail internally for the word line voltage, for DDR4 this need to be supplied externally. The required voltage on this rail is 2.5V. As per JEDEC specification, tolerance is ±250mV.

Reference Voltage:

While for DDR3, we have to provide VREF which is half of Operating voltage. For DDR4, there is no external voltage to be applied as this rail is generated internally.

ADDRESS, COMMAND, CLOCK signals and their termination:

ADDRESS, COMMAND, CLOCK signals doesn’t need external Termination. The memory chip does have internal termination and the I/O standard followed is SSTL-12.

DATA signals and their termination:

DDR4 has On-Die Termination and Dynamic ODT similar to DDR3. DDR4 Data bus including DATA lines, DATA STROBE, DATA MASK follows POD12 standard which is called as Pseudo open-drain standard.

ACTIVATE Signal:

ACT_N shall be used to determine the state of RAS_N/A16, CAS_N/A15, WE_N/A14.

When ACT_N = HIGH, these pins are treated as RAS_N, CAS_N, WE_N

When ACT_N = LOW, these pins are treated as A14, A15, A16

Bank Address and Bank Groups:

BANK ADDRESS, BANK GROUPS – In DDR4, the memory is divided into banks similar to DDR3. But in DDR4, there are additional bank groups of 4 numbers with each bank group comprising 4 banks totalling to 16 banks. So, we see BA 1:0 and BG 1:0 with 2 bits each helping to select the Bank Group and the corresponding Bank in it. These Bank address and bank groups fall under ADDRESS criteria and the same termination requirements stand.

Dynamic Bus Inversion (DBI):

Dynamic Bus Inversion is new to DDR4. The function of Dynamic Bus Inversion is to minimize the number of zeroes in the DATA so that there are less HIGH to LOW transitions and hence reduced switching noise and less power consumption. Dynamic Bus Inversion helps in Signal Integrity. DBI_N, UDBI_N, LDBI_N are the pins associated with this functionality. This can be applied to READ as well as WRITE.