As the industry is dominated by battery powered applications, it is important that designers plan their power budget and follow well planned strategies to reduce the power consumption in their boards.
If you have followed our previous post, this article is an extension to the same.
To optimize the power it is important that designer thinks at the overall system level and discuss with the stakeholders to plan a strategy. As a simple note, follow the below steps to optimize the power consumption.
- Selecting the lowest power consumption controllers is the important design criteria
- Most % of the embedded designs use a controller chip. There shall be several interfaces connected externally and GPIO pins connected. Also, there shall be some GPIO pins which are not connected. All the unused GPIO pins must be configured in output mode. After setting to output mode, The output must be set to zero. Disable all the pull-ups or pull-downs on the GPIO pins
- Clocking section is one of the power consumers in the controllers. We all know that entire controller internally runs n this clock. The clock frequency must be selected for the controller such that there is less power consumption. Selecting lower frequency is a straight forward option. The lowest frequency is definitely the RTC clock. There are other options like the internal oscillators which can be used. Clock frequency selection is always a trade off between Power Consumption and performance.
- If any particular interface (UART, I2C, SPI) is not used, ensure that those pins are not configured. However, ensure that this does not lead to frequency switching ON/OFF of logic. This leads to more power consumption.
- Configure the micro controller in a deep sleep modes whenever there is a IDLE operating conditions. If the interval between micro controller operations is very high, the controller instead of deep sleep mode can be switched OFF.
- Memory is another consumption of power in embedded circuits. Whenever, there is an external Flash or EEPROM in a circuit, use a MOSFET gate between it's power supply and input power. So, whenever READ and WRITE operations are done, using the gate circuit, disable the power to the external memory.
- Power conversion losses are unavoidable. For example, if you are using a Lithium-ion battery for powering your circuit, we have to convert the typical 3.7V input voltage to a 3.3V or 1.8V as per the need. If a switcher is used, the efficiency should be as high as possible to avoid losses.
- Select the major components such that the quiescent current is as low as possible
- It is suggested to operate the devices with an as low voltage as possible. this reduces the power consumption
- Ensure that there are not many power conversions in the circuit. For this, considering the majority of devices, operate with 3.3V, it is preferred that only 3.3V rail is on the board
- Dynamic voltage scaling (DVS) is one of the options that can be considered where the voltage can be switched based on the operations
- Avoid unnecessary power banks in the design like having a high capacitors on the board.
- Use the latest wireless technologies in your designs. As the technologies improved, the power consumption has also reduced.
The quiescent current which is the leakage current under the respective OFF condition of a device is very crucial to power consumption. What this means is that Quiescent current is not avoidable and is always a power consumer. Understanding the static vs dynamic power consumption (Static is when there is no operation, dynamic when there are logical operations) of the circuit is also very crucial. Using the dynamic power management techniques to handle power is the real challenge for the designers.
We have tried to work on MSP432, to check it's LPM states and could achieve what was the lowest current mentioned in the datasheet. While this is worked out on an evaluation board, achieving the same in your circuits is a challenging task.
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