http://embeddeddesignblog.com/vias-PCB.html
For boards more than or equal to 2-layers you require vias to route the signals from one layer to another. Without vias you cannot imagine finishing routing of your PCB. The placement and dimensions of vias are very critical for power and signal integrity. For power there must be as many as possibl to help carry more current. For signals, the lesser the vias the better the signal integrity.
1.For vias on sigals of lower frequencies, the effect can be neglected. That is why for vias on I2C, SPI, UART and other control signals we need not bother about signal integrity.
2. Via on clock signals should be used only if unaviodable. Especially, at higher clock frequencies, they need to be eliminated.
3. Vias cause reflections and impedance mismatch. This is the reason why they should be avoided on high frequency signals like, USB, PCIe, SATA, etc. In this electronics era of denser boards, vias are unaviodable. In this case, ensure that there is no more than one via on the signals. Signals with more than one via need to be simulated and performance is ensured before taping out the PCB. Pre-Layout and Post-Layout analysis is must for high speed signals anyways.
4. when we say vias cause impedance mismatch, it is the inherent capacitive effect of vias that cause the mismatch. This is what causes reflections and signal integrity issues. When we say signal integrity issue, we are talking about longer delay, longer rise and fall times because of via.
5. vias form a critical role in the loss budget calculations. Estimating the losses associated with vias need to be carefully characterized.
6. As the number of vias increases, the cost of the board increases. Especially, with the blind, buried and back drilled vias, the cost of the board increases.
7. Through holes can be plated or non-plated. Plated vias have a copper layer from the top to bottom along the via.Called PTH, it is laser drilled and cheapest.
8. For small form factor boards/high-Desity boards (HDI), blind and buried vias are used to save space, else mostly designers prefer to have PTH on their boards. Debugging a PTH post PCB fabrication is impossible, only X-ray of the board is an option.
9. Let us assume there is a via to conenct from Top to 3rd layer in a 10-layer board. In this case, the extra stub from 3rd to 10th layer on the board causes signal integrity. so, for high speed boards, back drilling is done to avoid additional stub. 10. one point to remember is that the effect of via can be ignored, if it's electrical length is less than the rise time of the signal. This is where the high speed signal rise time come into picture.
11. The via can be characterized for simulation purposes using the 3D solver softwares like ADS, ANSOFT, etc.
12. Donot create smaller vias on your PCB, the fabrication houses may struggle to bring them in physical state. Most of the fab houses these days can fabricate upto 6mils of diameter. The outer ring or annular ring around the via is greater than 6 mils.
13. Vias can pass only restricted current. so, have sufficient vias on the power plane, to pass required current. Online claculators are available to calculate the via currents. The via current varies with size and temperature.
14. There are minimum requriements for via to traces or via to via or via to pins. Check with your fabricator before releasing the PCB Layout. DFM should always be done on the PCB before releasing. Some standards define creepage and clearance which need to be taken into consideration.
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