HBM4 — The Memory
Powering Next-Gen AI
JEDEC's latest standard doubles the interface, doubles the bandwidth, and reshapes how AI accelerators think about data.
(up to 2.8 TB/s in leading implementations)
(12 nm / 5 nm)
What is HBM4?
High Bandwidth Memory 4 (HBM4) is the fourth generation of the JEDEC HBM standard, officially released in April 2025 under specification JESD270-4. It represents the most significant architectural leap in the history of stacked DRAM — not an incremental speed bump, but a fundamental redesign of the memory interface itself.
Where previous generations used a 1024-bit wide interface, HBM4 doubles this to 2048 bits, delivering up to 2 TB/s of bandwidth per stack without requiring extreme per-pin clock speeds. Leading implementations from SK Hynix and Micron already exceed 2.8 TB/s by pushing pins beyond the JEDEC baseline.
The architectural breakthrough
The core innovation is simple but powerful: wider is better than faster. Instead of racing pin speeds (which raises heat and power consumption), HBM4 runs a 2048-bit bus at a moderate 8 Gb/s per pin. The result is twice the throughput of HBM3E with dramatically better bandwidth-per-watt — critical for gigawatt-scale AI data centres where every joule counts.
HBM4 also introduces 32 independent channels per stack (up from 16), each with two pseudo-channels, enabling finer-grained access parallelism. Capacity scales up to 64 GB per stack in 16-Hi configurations using 32 Gb die densities — matching the memory appetite of trillion-parameter AI models.
Power, reliability and compatibility
The specification introduces flexible voltage levels — VDDQ at 0.7 V, 0.75 V, 0.8 V, or 0.9 V and VDDC at 1.0 V or 1.05 V — letting system designers tune the power envelope for their thermal budget. This flexibility, combined with the wider bus running at lower frequencies, targets a 60% improvement in power efficiency per bit compared to HBM3E.
On the reliability front, HBM4 adds Directed Refresh Management (DRFM) for improved row-hammer mitigation, per-channel thermal and voltage telemetry, and enhanced ECC — all features demanded by hyperscalers running mission-critical AI workloads continuously.
Who is making it and where is it going?
Why it matters for electronics engineers
If you design AI inference cards, HPC boards, or any system pairing a processor with high-speed memory, HBM4 sets the new baseline for bandwidth budgets. Its backward compatibility with HBM3 controllers gives you a migration path, but the 2048-bit physical interface demands a completely new silicon interposer design — not a drop-in swap.
Watch the emerging SPHBM4 (Standard Package HBM4) work at JEDEC, which aims to bring HBM4 bandwidth to organic substrates using 4:1 serialization on 512 pins — potentially making high-bandwidth memory accessible without the cost and complexity of a silicon interposer.
The memory wall — the gap between how fast processors compute and how fast they can fetch data — has long been the limiting factor in AI scaling. HBM4 is the most aggressive engineering response to that problem yet, and it signals that memory architecture will remain a first-class concern alongside compute for the foreseeable future.
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