Schematic Review points/Best Practices

 

One of the responsibilities of a electronics engineer is to review the schematic of others. A list of points which can be used to review the schematic is a must. Here we are listing some of the common points used for schematic review:

General:

• Using the correct schematic template?
• Schematic has all the same sheet sizes
• Schematic has revision history notes
• Most designers prefer to have block diagram, check if any block diagram included and correctness of it
• Schematics have title sheets and all the information in the title sheet is correct?
• Reference designators are assigned as per sections and not scattered

Circuit level:

• Are proper MPN assigned to components?
• MPN vs Footprint verification
• Are test points included on the board to have 100% test coverage?
• Is there ESD protection provided at the sections exposed to users? Example: at connectors
• Is the BOM optimization done on the board?
• Logic levels between the ICs on the board are verified to be compatible?
• Does the ICs used on the boards have proper straps or not as per the datasheet requirements?
• Verify gain requirements of the operational amplifier requirements
• Is there a buffer/series resistor on the UART pin so that chip doesn't get powered from UART
• Current limiting resistors provided on the pins to ensure no damage to chips, example: especially when powered off board
• If board has stringent EMI/EMC requirements, ensure that connector SHIELD pins are properly Earthed. Example: USB connector SHIELD pins
• Are all the unused pins terminated properly? - PU or PD resistors on the unused pins?
• Give special considerations to JTAG signal connections. If an ARM JTAG standard debugger will be used, ensure pin out to connector is as per debugger requirement
• Capacitors have the proper voltage specification as per the applied voltage?
• Check that protection mechanisms are employed at the input of the circuit? - inrush protection, over voltage protection, short circuit protection
• Inductors have the saturation current checked?
• Check the power dissipation across series resistors in the schematic
• Polarized components are connected as per their polarity?
• Ensure that capacitors are connected in the schematic as per the PCB Layout placement requirements. High frequency capacitors near to pin followed by low frequency capacitors. PCB Layout engineers take schematic as reference for placement.
• LED series resistors are properly sized?
• Are the warnings in ERC ignored or considered?
• TX-RX connections are properly connected and not swapped?
• SDA-SCL properly connected and not swapped?
• Pull-ups added on the SDA, SCL lines of I2C interface
• No two I2C interfaces must have the same address
• Analog and digital grounds are properly connected? Through Inductor?
• Thermal calculations done for the regulator?
• Are any of the components used on the board are EoL or "Not recommended for new designs"?
• Verify the symbols on the board
• Ensure that thermal pad is included in the symbol
• Any connectors pin assignments on the board have mating verified with the cable pins
• Connections within the same page should not use off sheet connections. Just net labels should be used
• Regulator feedback resistors calculation
• Diodes connected as per polarity requirements. Example in the case of switching regulators output
• NP0/COG capacitors are used near crystals?
• Are crystal load capacitors properly sized?
• Signals to be length matched are indicated as notes in the schematic?
• Ensure that MPN are displayed for symbols for schematic for good readability
• Ensure that schematic drawing is snapped to grid properly
• Check the temperature ratings of the components and whether they meet the required board end application or not?
• Ensure that series resistors used on the power lines don't drop too much voltage. example: sense resistors
• Ensure that each power pin of the IC has decoupling capacitor
• Check the power sequencing requirements for the design and verify they are met or not?
• Give special preference to the RC circuit on RESET pin and timing requirements
• If any simulation performed on the circuit, verify the simulation results and see if recommendations are implemented or not
• If high speed signals are involved, ensure proper termination techniques are used
• Are differential signals named properly?
• Differential signals have directives in the schematics Example: USB signals
• Ensure no swap of differential P and N signals

Calculations:

• Check the power calculations of the board
• Check the derating analysis of the board

Error checks:

• Is the schematic passing ERC or DRC? - some tools use ERC terminology and some tools DRC
• Are the correct settings enabled in ERC?
• Are the warnings in ERC ignored or considered?