DDR memory interfacing - Part 4

This article is a continuation to the posts that we had on the DDR. In this article, we will talk about the two specifications of the DDR3 memory:

1. Memory configuration specification
2. What prefetch means?

Memory configuration specification

​​Rather than talking in general terms, we have considered the same DDR3 part (MT41J256M4) which we considered in the previous part of the article.

​​In the last article, we have read about the datasheet parameters of  MT41J256M4 which is a DDR3 SDRAM memory. In this part, we will continue exploring the several specifications mentioned in the datasheet.

When we look at the configuration in the datasheet, it is mentioned as following:

What does 32 Meg x 4 x 8 banks mean?

SDRAMs have memory arranged as multi-bank architecture and it has banks, rows and columns.

The following diagram shows the arrangement of the DDR memory.

Here, 32 Meg x 4 x 8 banks mean there are 8 banks with each bank size of 32M. The x4 in the above specification indicates the data byte size.

Here, the type of configuration is selected based on the memory controller options on the processor. One has to remember that more the bus width higher the access speed of the DDR.

What prefetch means?

The features talk about the prefetch architecture:

What does the highlighted feature “8n-bit prefetch architecture” mean in DDR?

Before talking about the prefetch architecture, we have to talk about the “Data word” size of a processor. Data word means the number of bits that can be transferred from memory or from processor in a single instruction cycle. Take the case of a 4-bit data width size; you can carry 8-bits in a single clock cycle. This is similar to the 32-bit or 64-bit data word size we talk about in PCs.

 Let us assume the row size of DDR as 4096bits and the interface is 8-bit. Then, the number of data words can be 4096/8 = 512 data words to be accessed.

As the data is to be accessed from rows and columns, while accessing the data, the address of data and columns have to be transferred.  But one advantage is that when we are accessing the row first during a data word, column address has to be shared as well but as row is already selected, column selection within a given row is very speed.

 In a prefetch buffer architecture, when a memory access occurs to a row the buffer collects some of the adjacent data words on the row and reads them out. In this case, what is happening is that you are in no need to send the column address again. But previously, every time the column address has to be shared.

DDR2 has 4n pre-fetch buffer which means 4 consecutive data words are read and placed in buffer. If you go one generation back, DDR1 could only prefetch two data words at a time. That means other than the intended data word, the consecutive one is also read. When we come to DDR3, the prefetch architecture is 8n, where 8 consecutive data words are read and placed in the buffer. This is the primary reason why the DDR3 has been able to communicate at a much faster data rate than previous generation memories.

 The above point clearly indicates that the prefetch buffer size of the DDR3 is 8 times more than DDR1. Also, the prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency.