XAUI Interface - A small note

As the speeds across the Ethernet increase without bounds, it is the effort of the design engineers that is very crucial to it's success. In Ethernet interfaces, now a days, we talk about the 10G, 40G and the 100G speeds. These speeds have been putting lot of constraints at the chip level as well as at the interface connectivity side. Physical connectivity is another challenge in these scenarios. We know about the MII, RGMII and SGMII interfaces which are more of the standards that are used at the below 10G ranges. When you reach the 10G speeds, it is the XGMII interface that needs to be considered. The XGMII when you speak in terms of signals is a heavily stuffed interface.In this interface, there are around 32-bit lines for the Tx and Rx and which is subdivided again into the Tx lines with each byte section. Basically, the signalling interface for the XGMII looks as below:

With as many as 66 signals as shown in the table it is always a huge effort for the layout engineer to come up with the routing of these signals. So, an extender is definitely required which helps designers to abstract the XGMII from the external world and make the designers work easy. This is where the XGXS sub layer comes into consideration. The output of this sub-layer is a serial differential interface with minimized signal count. This is called the XAUI interface. The XAUI interface signals are as follows:

We can clearly see that with the XGXS sub-layer, the 10G interface for the designers has been simplified to a simple serial differential pairs which is much easier for the layout engineer to handle. This XGXS sub-layer when simplified into a small block diagram looks likes as below:

Now, after talking all about this XGXS stuff, we forgot about the actual need for XGMII interface. We know that MII, RGMII, SGMII are MAC to PHY interfaces. Similar to them, XGMII is also MAC to PHY interface, but actually, it is the XAUI interfaces that acts as the interface between MAC and PHY. So, now we clearly know that when take a processor or an Ethernet switch with 10G interface, it is actually the XAUI that we connect for achieving 10G interface. This meant that there is XGXS interface inside the Ethernet switch (MAC side), so, similarly, at the PHY side, XGXS is again required.

Now, after all this discussion, it is clear that XAUI is a standard for extending the XGMII between the MAC and PHY.

Other important points about XAUI interface:

• XAUI is a chip-to-chip interface, backplane interface
• XAUI is a full-duplex interface
• XAUI interface is self-clocked. This means there is no need of separate clock signals
• Differential impedance of 100 ohms
• Data rate of each differential pair is 3.125Gbps
• Differential voltage of 1600mVp-p
• Uses 8b/10b encoding
• The length matching requirement of signals in each pair is very critical

Chips in the market:

TLK3114SC - XAUI transceiver from Texas Instruments