MediaTek has just claimed a major manufacturing milestone: the Dimensity 9600 Pro is the first announced smartphone chipset built on a 2nm process node, and it ships with an architecture explicitly designed around agentic AI on-device systems that can perceive, reason, and act, rather than simply answer prompts. For anyone tracking where mobile silicon is headed, this launch is worth a closer technical look.
Why 2nm Matters
Process node shrinks aren't just marketing numbers they translate directly into transistor density, switching speed, and power draw. Moving from the 3nm-class nodes used in the previous Dimensity 9500 generation down to 2nm lets MediaTek pack more compute into the same silicon footprint while cutting leakage current.
The real-world payoff MediaTek is advertising is a 61% drop in multi-core power consumption compared to its predecessor, alongside modest but real CPU gains roughly 17% higher single-core and 15% higher multi-core performance. That efficiency headroom is what makes the chip's more ambitious AI claims plausible: running large models on a phone is as much a power-budget problem as a raw-compute one.
The CPU itself uses a 4th-generation All Big Core design in a 2+3+3 configuration: two high-clock "Ultra" cores up to 4.55GHz, three performance cores at 4.35GHz with more L2 cache, and three efficiency-leaning performance cores at 3.1GHz. That's paired with a larger cache hierarchy — 16MB of L3 and a 10MB system-level cache which matters a lot for keeping large AI models fed with data without constantly hitting slower main memory.
Dual-NPU Architecture: Splitting "Always-On" from "Heavy Lifting"
The more interesting design decision, from an engineering standpoint, isn't the CPU it's the dual-NPU split:
NPU 1090 is the high-throughput engine, built for generative and agentic workloads. MediaTek reports a 51% improvement in LLM prefill performance and 55% better tokens-generated-per-watt versus the prior generation, along with doubled INT4 compute throughput.
Super Efficient NPU 2.0 is a smaller, always-on companion processor dedicated to background AI tasks — context monitoring, sensor fusion, wake-word and scene detection cutting power for these persistent tasks by roughly 40%.
This is a meaningful architectural pattern, not just a spec bump. Running a single large NPU continuously to watch for triggers would drain a battery fast; offloading that "always listening/watching" role to a dedicated low-power engine, while reserving the big NPU for burst inference, is the same big.LITTLE philosophy CPUs have used for years now applied to neural accelerators.
On-Device LLMs Up to 30B Parameters
The headline capability is support for on-device large language models up to 30 billion parameters. For context, most 2025-era flagship chips were realistically tuned for sub-10B models running locally, with anything larger routed to the cloud. Getting to 30B on-device is a substantial jump, made possible by three things working together:
Memory bandwidth the chip adds support for LPDDR6, which is necessary because large model inference is often memory-bandwidth bound, not just compute bound.
Storage throughput industry-first support for UFS 5.0 speeds up model loading and swapping.
Model compression and Mixture-of-Experts (MoE) support the NPU architecture is built to run compressed and MoE-style models, where only a subset of a large model's parameters activate per inference step, reducing effective compute and memory load versus a dense 30B model.
Practically, this means a phone could run a meaningfully capable local model for tasks like summarization, planning, or multi-step reasoning without a network round-trip to a cloud API improving both latency and privacy, since raw data doesn't have to leave the device.
What "Agentic AI Engine" Actually Changes for Phone Use
MediaTek's framing is that the phone stops being a device that waits for input and becomes one that runs a persistent background agent observing app state, notifications, and context, and proactively acting or suggesting actions. The AI Compute Fusion Architecture is the software/hardware layer coordinating this: it lets the CPU, NPU, and the chip's scheduling engine share workloads dynamically so multiple "agents" or background AI tasks can run concurrently without one starving another of resources or blowing the power budget.
Concretely, this architecture is aimed at things like:
Proactive assistance — the phone surfacing relevant information or actions based on inferred intent, rather than a user issuing a command.
Cross-app coordination — an agent that can act across multiple apps (e.g., pulling data from messaging into a calendar action) without each app needing bespoke integration.
On-device personalization — a "digital twin"-style model that adapts to a user's patterns locally, rather than requiring cloud-side profile syncing.
The GPU and NPU are also fused for what MediaTek calls a Neural Graphics Architecture, and the ISP taps directly into NPU intelligence for computational photography signaling that "AI acceleration" on this chip isn't siloed to a chatbot feature, but threaded through imaging and graphics pipelines too.
The Bigger Picture
This launch puts MediaTek ahead of Qualcomm in reaching a 2nm-class node for a shipping mobile SoC, and reporting suggests it's priced more aggressively than Apple's 2nm A20 Pro, which remains exclusive to Apple's own hardware. If on-device 30B-parameter inference performs as advertised in real phones not just lab benchmarks — it would mark a real inflection point: the difference between a phone that calls out to an LLM API and one that is the inference endpoint.
The caveats are the usual ones for any chip launch: MediaTek hasn't yet named which phones will ship with the Dimensity 9600 Pro, and sustained performance, thermals, and real battery life under actual agentic workloads can only be judged once devices are in hand later this quarter. Peak NPU throughput and marketing benchmarks rarely survive contact with all-day, real-world use unchanged.