How to Configure GPIO Falling Edge Interrupts in BGM220P module (Step-by-Step Guide)

Before jumping into any code, firmware engineer has to work on steps required for configuring the microcontroller or module like BGM220P. Then using the steps listed, configure the corresponding registers of the desired module/microcontroller.

Below are the steps required. Firmware engineering world call it algorithm.

1. Enable peripheral clock
Turn on the clock for the GPIO port (and interrupt controller, if separately gated).

2. Select and Configure the pin as input
Select the pin for which falling edge interrupt can be configured. Set the target pin's mode register to input mode.

3. Configure pull resistor (optional but common)
If the signal floats when idle, enable an internal pull-up or pull-down so the pin has a defined "high" resting state before the falling edge occurs. If your board has on-board pull-up, you can ignore this.

4. Select edge-trigger type
In the interrupt/EXTI configuration register, set the trigger for that pin to falling edge (as opposed to rising, both, or level-triggered).

5. Map the pin to an interrupt line
On some MCUs (e.g., STM32 EXTI), you must explicitly connect the GPIO pin to its corresponding external interrupt line/channel.

6. Enable the interrupt at the peripheral level
Unmask the interrupt for that specific pin/line in the interrupt mask register.

7. Enable the interrupt in the NVIC / global interrupt controller
Enable the corresponding IRQ in the CPU's interrupt controller and set a priority level.

8. Enable global interrupts
Make sure the CPU's global interrupt enable flag is set (often done once at startup).

9. Write the ISR (Interrupt Service Routine)

• Check/clear the interrupt pending flag first (many MCUs require this, or the ISR will re-trigger immediately).
• Keep the ISR short — do minimal work (e.g., set a flag, read a value) and defer heavy processing to the main loop.

10. Test with debounce consideration
Mechanical switches bounce; add a debounce (hardware RC filter or software timer check) if the falling edge comes from a button rather than a clean digital signal.

Pseudocode: PC7 Falling Edge Interrupt on BGM220P (EFR32BG22-based)

// 1. Enable GPIO clock

CMU_ClockEnable(cmuClock_GPIO, true);

// 2. Configure PC7 as input (with pull-up, since falling edge needs a defined HIGH idle state)

GPIO_PinModeSet(gpioPortC, 7, gpioModeInputPull, 1);

//   Args: port, pin, mode, initial DOUT (1 = pull-up enabled)

// 3. Configure external interrupt on PC7

//    - Selects PC7 as the source for its interrupt line

//    - Enables falling edge trigger, disables rising edge

GPIO_ExtIntConfig(gpioPortC, 7, 7, false, true, true);

//   Args: port, pin, intNo (usually = pin number), risingEdge=false,

//         fallingEdge=true, enableInt=true

// 4. Clear any pending interrupt flag before enabling NVIC

GPIO_IntClear(1 << 7);

// 5. Enable the GPIO interrupt in NVIC

//    Series 2 devices split GPIO interrupts into EVEN/ODD lines

NVIC_ClearPendingIRQ(GPIO_ODD_IRQn);   // PC7 is odd-numbered pin

NVIC_EnableIRQ(GPIO_ODD_IRQn);

// 6. Global interrupt enable

__enable_irq();

// 7. Interrupt Service Routine

void GPIO_ODD_IRQHandler(void)

{

    uint32_t flags = GPIO_IntGet();     // Read pending flags

    GPIO_IntClear(flags);               // Clear immediately

    if (flags & (1 << 7)) {

        // PC7 falling edge event handling

        // Keep short — set a flag, wake main loop, etc.

    }

}