Schematic Design Review Checklist

Power System - Verify safe, stable, and correct power generation and distribution.

•  All power rails labeled clearly (+5V, +3.3V, VBAT, etc.).
•  Input power source (USB, DC jack, battery, etc.) clearly defined.
•  Reverse-polarity and overcurrent protection included (diode, fuse, ideal diode FET).
•  Voltage regulators correctly configured (IN/OUT/EN/FB pins connected, resistor dividers correct).
•  Decoupling capacitors on each rail (100 nF near every IC VCC pin, 4.7–10 µF bulk per regulator).
•  Adequate power filtering (LC or RC filters for sensitive analog rails).
•  Power LED and test points present on major rails.
•  Grounding scheme defined (single ground symbol or separated AGND/DGND with tie point).
•  Power sequencing, enable signals, or resets considered if multiple rails.
•  Expected current per rail verified vs regulator rating.

Connectors & Interfaces - Ensure all external connections are clear, keyed, and protected.

•  All connectors labeled with signal names, orientation, and pin numbers.
•  Matching mating part or footprint verified.
•  Unused pins are marked “NC” or tied properly.
•  Input/output direction defined in net labels or documentation.
•  ESD protection (TVS diodes, RC filters) for external connectors.
•  Ground reference pin on each external connector.
•  Mechanical stability (mounting holes, locking headers, etc.).
•  Clear labeling of connector function in schematic notes (e.g., “To Water Level Sensor”).

Protection & Reliability - Protect circuitry from electrical and environmental hazards.

•  ESD/EMI protection on external lines (TVS, ferrite bead).
•  Series resistors or RC snubbers on signal lines prone to ringing or long cables.
•  Reverse polarity protection on power inputs.
•  Overcurrent protection (polyfuse, current limit IC).
•  Lightning / surge protection if outdoor or industrial.
•  Input clamp diodes on analog or ADC lines.
•  Flyback diodes across inductive loads (relays, motors, solenoids).
•  Isolation (optocouplers, digital isolators, transformers) if needed between power domains.

Signal Integrity & Noise - Minimize noise coupling and ensure clean analog/digital performance.

•  Analog and digital grounds separated and tied at a single point if needed.
•  Sensitive analog traces have low-impedance return paths.
•  Decoupling and bulk caps placed near devices.
•  Filtering (RC, LC, ferrite) used for noisy supplies or sensitive analog nodes.
•  High-speed signals (I²C, SPI, UART) have series termination resistors if needed (22–100 Ω).
•  Long cable lines have RC/TVS protection.
•  Clock lines kept short and impedance-controlled (if high frequency).
•  Analog inputs protected with resistors and clamps to rails.

Clock & Timing - Ensure stable, reliable timing sources for all ICs.

•  Oscillator or crystal specifications meet IC requirements.
•  Load capacitors for crystal match datasheet values.
•  Clock trace lengths minimized and routed cleanly (short, direct, symmetric).
•  Optional provision for external clock or test clock input.
•  Enable or power-down pins properly tied.
•  Clock source startup time verified if MCU or ADC requires it.

Microcontroller / Digital Logic - Confirm all digital devices have correct support circuitry.

•  All VCC and GND pins connected.
•  Decoupling caps at each VCC pin.
•  Reset circuit implemented (manual reset switch, pull-up, capacitor if needed).
•  Boot or mode pins tied correctly (BOOT0, MODE, etc.).
•  Programming connector present and labeled (SWD, UART, ICSP).
•  Pull-ups/pull-downs added as required by datasheet.
•  I/O voltage levels match peripheral logic levels.
•  Clock/oscillator connected as per datasheet.
•  All unused pins defined (input/pulled, not floating).

Analog / Sensor Inputs - Ensure accuracy, linearity, and protection of analog signals.

•  Input range within ADC limits (Vref, rails).
•  Series resistor and RC filter on each analog channel.
•  Sensor power supply filtered and stable.
•  Reference voltage (Vref) decoupled and isolated.
•  Protection diodes or clamps for out-of-range inputs.
•  Sensor biasing (pull-ups/pull-downs) as per sensor specs.
•  Provisions for calibration (jumpers, trimmers).
•  Label all analog nets clearly.

Communication Interfaces (I²C, SPI, UART, etc.) - Ensure proper connectivity and bus integrity.

•  Bus lines labeled consistently across sheets.
•  Pull-ups on I²C SDA/SCL (typically 4.7k–10k).
•  Level shifting if voltage domains differ.
•  Chip selects on SPI defined and unique.
•  UART TX/RX cross-checked (no inversion).
•  Optionally add series resistors (33–100 Ω) on high-speed digital lines.
•  ESD protection for external communication ports.
•  Test headers or debug pads for key interfaces.

Mechanical & Layout Considerations - Prepare schematic for a physically manufacturable layout.

•  All components have valid footprints and orientations verified.
•  Connectors and large parts positioned logically (edges, alignment).
•  Mounting holes shown and grounded if required.
•  Board outline and mechanical keepouts defined.
•  Power and signal flow logically follow left-to-right, top-to-bottom.
•  Component values realistic for placement (package sizes, clearances).
•  Thermal considerations noted for regulators/power devices.

Documentation & Metadata - Ensure traceability and readiness for manufacturing.

•  Title block filled (project name, revision, author, date).
•  Version control tags (Git revision or sheet version) noted.
•  All components annotated uniquely (no duplicate references).
•  Component fields filled (Value, Footprint, Datasheet).
•  Notes for test points, calibration, jumpers.
•  Net labels consistent and descriptive.
•  Design references to datasheets included where relevant.

Test & Debug Provisions - Facilitate validation, debugging, and maintenance.

•  Test points on major rails (VCC, GND, signals).
•  Breakout header or pin for serial/debug access.
•  Status LEDs for power, communication, or faults.
•  Optional measurement jumpers or 0Ω links for isolation.
•  Clear labeling of test functions in schematic notes.

EMC / EMI / Environmental - Prepare for compliance and real-world robustness.

•  Input filtering (ferrite beads, common-mode chokes where needed).
•  Ground planes planned for return paths.
•  Shielding or ground guard traces for high-impedance analog signals.
•  Proper decoupling at all ICs.
•  Transient suppression near external cables.
•  Consider conformal coating, moisture sealing, or sensor isolation (if environmental).

Final Validation - Verify readiness for layout and fabrication.

•  ERC passes without unconnected pins (ignore only intentional ones).
•  Power consumption estimated vs source capability.
•  Reference voltages and analog ranges validated.
•  Design reviewed by at least one other engineer (peer check).
•  Schematic version frozen before layout.
•  Design notes exported with BOM and netlist for traceability.