High speed Designs - Part 25 (Creating VRM model of a LDO for Hyperlynx simulation)

High speed Designs - Part 25 (Creating VRM model of a LDO for Hyperlynx simulation)

We create a VRM model of the regulator in Hyperlynx for the power source for Power Integrity simulations. We need to generate a lumped equivalent circuit. Let us look at creation of VRM model for TLV7A03.

The TLV7A03 is an ultra-small, ultra-low quiescent current low-dropout linear regulator (LDO) that sources 200mA with excellent transient performance.

The first requirement is to get the step load for the LDO. Below is the load transient response of the LDO from the datasheet.

Get the output capacitor value as recommended by the LDO datasheet. Datasheet recommends a 1uF output capacitor for excellent transient response. This capacitor will anyway comes form your design.

Calculate the di/dt:
From the above graph, the current rise to 200mA within the 5 us.So, it is 0.2A/5us


Variation of the VOUT on load transient:
The VOUT varies up to 100mV on a sudden load transient which actually looks huge variation.


Inductance can be calculated using the equation, V = L* (di/dt)

L = V/(di/dt) = 100m/(0.2/0.000005) = 2.5uH

Rise Time of the output pulse:
The rise time of the output is ~4uS.

Calculate the Series Resistance:
Series resistance of the output, Rout = L/(1.5*tr)

Rout = 2.5u/(1.5*4u) = 2.4 ohms

VRM model:
VRM model (lumped equivalent circuit) now looks like,


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