DDR memory interfacing - Part 5

Let us look at how Column Latency of DDR2 and DDR3 compare from their datasheets.

Here are two snapshots of Dual data rate (DDR) Random access memories (RAM) timing parameters.

The below is from the DDR2 memory from Micron (MT47H256M4).

The below is from the DDR3 memory from Micron (MT41J256M4).

Considering -187E model for our discussion, this has common clock speed of 533MHz.

With 533MHz clock, as data is clocked on both edges we see from above table that data transfer rate is 533*2 = 1066MHz.

At this clock rate, the column Latency (CL) for both the devices is 7.

Column latency (or Column Access Strobe (CAS) latency) is nothing but the time taken by the DDR memory to respond after the issue of read command by DDR controller of processor. Here respond meant data must be available on the DDR pins.

We observe that as the data rate is increased in DDR3, the CL value increases. This meant that even though clock has increased, there isn't that much expected increase in speed of operation (of course there is!!)

But one may ask, DDR3 is costly too, then what advantage DDR3 is giving me compared to DDR2? For this, we should not forget that DDR3 power consumption is less and have several other features like Automatic self refresh (ASR) and Write leveling.​