Clock is one of the important signal in a modern day electronics systems. A clock is ideally a square wave. but in real time, due to lot of constraints it is never a square wave, especially at higher frequencies. When we see the frequency plot of this square wave (not exactly a square), we can see different frequencies of varying amplitude. For a low frequency signal, where the rise time is comparatively high, the harmonic amplitude is less and it is viceversa.
Consider a mobile/tablet PCB where you will be having clocks of different frequencies. An I2C may be operating up to 1MHz, SPI around 50MHz range, a DDR operating on a very high frequency, can be up to 666MHz, eMMC operating upto 54MHz and so on. You can see that the frequency of clock is varying as per the interface. So, the design guidelines for each interface varies. We can use an internal PLL in processor for this clocks generation or a external clock distribution devices. Whatever, the clock may get effected by the following problems:
1. Attenuation because of PCB traces
2. Pulse edge distortion
3. Jitter because of impedance mismatch and ringing (undershoot/overshoot)
4. Skew and phase difference
5. Cross Talk
6. EMI
A board Designer must take following precautions to avoid above conditions:
1. Use high swing clock signals
2. Chose proper termination technique to achieve impedance matching and hence eliminate reflections (power dissipation also to be considered)
Also, during layout, following guidelines need to be taken:
1. Place the clock source as close as possible to the device. to say it the other way, use short PCB traces.
2. Avoid using vias for clock. Vias cause impedance mismatch and hence reflections.
3. If the clock is routed on outer layer, take care that it has a reference plane next to it.
4. Route the signal in the inner layers to avoid EMI. The inner layer must be sandwiched by reference planes.
5. Avoid routing clock on different signal layers.
6. Keep the traces as straight as possible. In case of any bend required, do not use right angle bends. Use either 45 degree or arcs.
7. For a differential clock, the distance between P/N must be thrice the height of dielectric. this space must be maintained over the entire routing length.
8. Length matching must be there between P/N, else it results in skew and phase difference.
9. If same clock need to be used for more than one device, avoid using stubs. Instead prefer, daisy chaining or star routing (T topology). The devices to which clock is routed may not be at equal distance from clock source. In this case, use a serpentine routing to match the length.
10. To avoid crosstalk, the distance between two differential pairs must be twice the distance between P&N of individual pair.
More to follow in next article....
Consider a mobile/tablet PCB where you will be having clocks of different frequencies. An I2C may be operating up to 1MHz, SPI around 50MHz range, a DDR operating on a very high frequency, can be up to 666MHz, eMMC operating upto 54MHz and so on. You can see that the frequency of clock is varying as per the interface. So, the design guidelines for each interface varies. We can use an internal PLL in processor for this clocks generation or a external clock distribution devices. Whatever, the clock may get effected by the following problems:
1. Attenuation because of PCB traces
2. Pulse edge distortion
3. Jitter because of impedance mismatch and ringing (undershoot/overshoot)
4. Skew and phase difference
5. Cross Talk
6. EMI
A board Designer must take following precautions to avoid above conditions:
1. Use high swing clock signals
2. Chose proper termination technique to achieve impedance matching and hence eliminate reflections (power dissipation also to be considered)
Also, during layout, following guidelines need to be taken:
1. Place the clock source as close as possible to the device. to say it the other way, use short PCB traces.
2. Avoid using vias for clock. Vias cause impedance mismatch and hence reflections.
3. If the clock is routed on outer layer, take care that it has a reference plane next to it.
4. Route the signal in the inner layers to avoid EMI. The inner layer must be sandwiched by reference planes.
5. Avoid routing clock on different signal layers.
6. Keep the traces as straight as possible. In case of any bend required, do not use right angle bends. Use either 45 degree or arcs.
7. For a differential clock, the distance between P/N must be thrice the height of dielectric. this space must be maintained over the entire routing length.
8. Length matching must be there between P/N, else it results in skew and phase difference.
9. If same clock need to be used for more than one device, avoid using stubs. Instead prefer, daisy chaining or star routing (T topology). The devices to which clock is routed may not be at equal distance from clock source. In this case, use a serpentine routing to match the length.
10. To avoid crosstalk, the distance between two differential pairs must be twice the distance between P&N of individual pair.
More to follow in next article....
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